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elitemt m11l416256sa dram 256 k x 16 dram edo page mode features x16 organization edo (extended data-output) access mode 2 cas byte/word read/write operation single 3.3v ( 10%) power supply lvttl-compatible inputs and outputs 512-cycle refresh in 8ms refresh modes : ras only, cas before ras (cbr) and hidden capabilities self-refresh capability jedec standard pinout elite memory technology inc publication date : aug. 2005 revision : 1.4 1/16 key ac parameter t rac t cac t rc t pc -35 35 10 65 14 ordering information - package 40-pin 400mil soj 44 / 40-pin 400mil tsop (type ii) product no. packing type comments m11l416256sa- 35 tg m11l416256sa- 35 jp soj/tsopii pb-free general description the m11l416256 series is a randomly accessed solid state me mory, organized as 262,144 x 16 bits device. it offers extended data-output , 3.3v( 10%) single power supply. access time (-35) , self-refresh and package type (soj, tsop ii) are optional features of this family. all these family have cas - before - ras , ras -only refresh and hidden refresh capabilities. two access modes are supported by this device: byte access and word access. use only one of the two cas and leave the other staying high will result in a byte access. word access happens when two cas ( casl , cash ) are used. casl transiting low during read or write cycle will outpu t or input data into the lower byte (io0~io7), and cash transiting low will output or input data into the upper byte (io8~15). pin assignment soj top view tsop (typeii) top view 1 2 3 4 5 6 7 8 9 v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 40 39 38 37 36 35 34 33 32 v ss i/o15 i/o14 i/o13 i/o12 v ss i/o11 i/o10 i/o9 10 11 12 13 14 15 16 17 18 19 20 i/o7 nc nc we ras nc a0 a1 a2 a3 v cc 31 30 29 28 27 26 25 24 23 22 21 i/o8 nc casl cash oe a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 v cc i/o0 i/o1 i/o2 i/o3 v cc i/o4 i/o5 i/o6 i/o7 nc nc we ras nc a0 a1 a2 a3 v cc 40 39 38 37 36 35 34 33 32 31 v ss i/o15 i/o14 i/o13 i/o12 v ss i/o11 i/o10 i/o9 i/o8 nc casl cash oe a8 a7 a6 a5 a4 v ss 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21
elitemt m11l416256sa functional block diagram control logic data-in buffer clock generator data-out buffer column address buffer refresh controler refresh counter row. address buffers(9) 9 a0 a1 a2 a3 a4 a5 a6 a7 column decoder oe 16 row decoder 512 x 512 x 16 memory array 16 sense amplifiers i/o gating 8 512 x 16 v cc v ss io0 : io15 ras cash 512 512 9 9 9 9 9 casl v bb generator we 16 a8 pin descriptions pin no. pin name type description 16~19,22~26 a0~a8 input address input row address : a0~a8 column address : a0~a8 14 ras input row address strobe 28 cash input column address strobe / upper byte control 29 casl input column address strobe / lower byte control 13 we input write enable 27 oe input output enable 2~5,7~10,31~34,36~39 i/o0 ~ i/o15 input / output data input / output 1,6,20 v cc supply power, 3.3v 21,35,40 v ss ground ground 11,12,15,30 nc - no connect elite memory technology inc publication date : aug. 2005 revision : 1.4 2/16
elitemt m11l416256sa absolute maximum ratings voltage on any pin relative to vss ? ??-0.5v to +4.6v operating temperature, t a (ambient) ?.0 to +70 c c storage temperature (plastic) ???.-55 to +150 c c power dissipation ?????????????0.8w short circuit output current ????????50ma permanent device damage may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation of the device above those conditions indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and recommended operating conditions (0 t a 70 ; v cc = 3.3v c c 10% unless otherwise noted) parameter conditions symbol min max units notes supply voltage v cc 3.0 3.6 v 1 supply voltage v ss 0 0 v input high voltage v ih 2.0 v cc +0.3 v 1 input low voltage v il -0.3 0.8 v 1 input leakage current 0v v in v ih (max) i li -10 10 a output leakage current 0v v out v cc output(s) disable i lo -10 10 a output high voltage i oh = -2 ma v oh 2.4 - v output low voltage i ol = 2 ma v ol - 0.4 v note : 1.all voltages referenced to v ss max parameter conditions symbol -35 units notes operating current ras , cas cycling , t rc =min i cc1 150 ma 1,2 ttl interface , ras , cas = v ih , d out =high-z 4 ma standby current cmos interface, ras , cas v cc -0.2v i cc2 2 ma ras only refresh current t rc = min i cc3 150 ma 2 edo page mode current t pc = min i cc4 150 ma 1,3 standby current ras =v ih , cas = v il i cc5 5 ma 1 cas before ras refresh current t rc = min i cc6 150 ma battery backup current (s-ver. only) ras , cas 0.2v, d out = high-z, cmos interface i cc7 400 a self refresh current (s-ver. only) ras = cas = v il , we = oe = a0~a8 = v cc -0.2 or 0.2v dq0~dq15 = v cc -0.2, 0.2v or open i cc8 400 a note : 1. i cc max is specified at the output open condition. 2. address can be changed twice or less while ras =v il . 3. address can be changed once or less while cas =v ih . elite memory technology inc publication date : aug. 2005 revision : 1.4 3/16
elitemt m11l416256sa capacitance (ta = 25 , v cc = 3.3v 10%) c parameter symbol typ max unit input capacitance (address) c i1 - 5 pf input capacitance ( ras , cash , casl , we , oe ) c i2 - 7 pf output capacitance (i/o0~i/o15) c i / o - 10 pf ac electrical characteristics (ta = 0 to 70 , v cc =3.3v c 10%, v ss = 0v) (note 14) test conditions input timing reference levels : 0.8v, 2.0v output reference level : v ol = 0.8v, v oh =2.0v output load : 2ttl gate + cl (50pf) assumed t t = 2ns -35 parameter symbol min max unit notes read or write cycle time t rc 65 ns read write cycle time t rwc 95 ns edo-page-mode read or write cycle time t pc 14 ns 22 edo-page-mode read-write cycle time t pcm 42 ns 22 access time from ras t rac 35 ns 4 access time from cas t cac 10 ns 5,20 access time from oe t oac 10 ns 13,20 access time from column address t aa 18 ns access time from cas precharge t acp 20 ns 20 ras pulse width t ras 35 10k ns ras pulse width (edo page mode) t rasc 35 100k ns ras hold time t rsh 10 ns 25 ras precharge time t rp 25 ns cas pulse width t cas 5 10k ns 24 cas hold time t csh 30 ns 19 cas precharge time t cp 5 ns 6,23 ras to cas delay time t rcd 10 25 ns 7,18 cas to ras precharge time t crp 5 ns 19 row address setup time t asr 0 ns row address hold time t rah 5 ns ras to column address delay time t rad 8 17 ns 8 column address setup time t asc 0 ns 18 column address hold time t cah 5 ns 18 column address hold time (reference to ras ) t ar 30 ns column address to ras lead time t ral 18 ns read command setup time t rcs 0 15,18 elite memory technology inc publication date : aug. 2005 revision : 1.4 4/16
elitemt m11l416256sa (continued) -35 parameter symbol min max unit notes read command hold time reference to cas t rch 0 ns 9,15,19 read command hold time reference to ras t rrh 0 ns 9 cas to output in low-z t clz 3 ns 20 output buffer turn-off delay from cas or ras t off1 3 15 ns 10,17,20 output buffer turn-off to oe t off2 8 ns 17,26 write command setup time t wcs 0 ns 11,15,18 write command hold time t wch 5 ns 15,25 write command hold time(reference to ras ) t wcr 30 ns 15 write command pulse width t wp 5 ns 15 write command to ras lead time t rwl 9 ns 15 write command to cas lead time t cwl 7 ns 15,19 data-in setup time t ds 0 ns 12,20 data-in hold time t dh 5 ns 12,20 data-in hold time (reference to ras ) t dhr 30 ns ras to we delay time t rwd 51 ns 11 column address to we delay time t awd 34 ns 11 cas to we delay time t cwd 26 ns 11,18 transition time (rise or fall) t t 2.5 50 ns 2,3 refresh period (512 cycles) t ref 8 ms ras to cas precharge time t rpc 10 ns cas setup time(cbr refresh) t csr 10 ns 1,18 cas hold time(cbr refresh) t chr 10 ns 1,19 oe hold time from we during read-mode-write cycle t oeh 4 ns 16 oe low to cas high setup time t oes 4 ns oe high hold time from cas high t oehc 2 ns oe precharge time t oep 2 ns oe setup prior to ras during hidden refresh cycle t ord 0 ns last cas going low to first cas returning high t clch 5 ns 21 data output hold after cas returning low t coh 3 ns output disable delay from we t whz 3 7 ns self refresh ras low pulse width t rass 100 s 27,28 self refresh ras high precharge time t rps 65 ns 27,28 self refresh cas hold time t chs -50 ns 27,28 elite memory technology inc publication date : aug. 2005 revision : 1.4 5/16
elitemt m11l416256sa notes : 1. enables on-chip refresh and address counters. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il . 3. in addition to meet the transition rate specification, all input signals must transit between v ih and v il in a monotonic manner. 4. assume that t rcd < t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 5. assume that t rcd t rcd (max) 6. if cas is low at the falling edge of ras , data-out will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, cas and ras must be pulsed high. 7. operation within the t rcd limit ensures that t rcd (max) can be met, t rcd (max) is specified as a reference point only ; if t rcd is greater than the specified t rcd (max) limit, access time is controlled by t cac . 8. operation within the t rad limit ensures that t rad (max) can be met. t rad (max) is specified as a reference point only ; if t rad is greater than the specified t rad (max) limit, access time is controlled by t aa . 9. either t rch or t rrh must be satisfied for a read cycle. 10. t off1 (max) defines the time at which the output achieves the open circuit condition ; it is not a reference to v oh or v ol . 11. t wcs , t rwd , t awd and t cwd are restrictive operating parameters in late write and read-modify-write cycle only. if t wcs t wcs(min) , the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. if t rwd t rwd(min) , t aw d tawd(min) and t cwd t cwd(min) , the cycle is read-write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of i/o (at access time and until cas and ras or oe go back to v ih ) is indeterminate. oe held high and we taken low after cas goes low result in a late write ( oe -controlled) cycle. 12. those parameters are referenced to cas leading edge in early write cycles and we leading edge in late write or read-modify- write cycles. 13. during a read cycle, if oe is low then taken high before cas goes high, i/o goes open, if oe is tied permanently low, a late write or read-modify-write operation is not possible. 14. an initial pause of 200 s is required after power-up followed by eight ras refresh cycles ( ras only or cbr) before proper device operation is assured. the eight ras cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 15. write command is defined as we going low. 16. late write and read-modify-write cycles must have both toff2 and t oeh met ( oe high during write cycle) in order to ensure that the output buffers will be open during the write cycles. 17. the i/os open during read cycles once t off1 or t off2 occur. 18. referenced to the earlier cas falling edge. 19. referenced to the latter cas rising edge. 20. output parameter (i/o) is referenced to corresponding cas input, io0~7 by casl and io8~15 by cash . 21. last falling cas edge to first rising cas edge. 22. last rising cas edge to next cycle?s last rising cas edge. 23. last rising cas edge to first falling cas edge. 24. each cas must meet minimum pulse width. 25. referenced to the latter cas falling edge. 26. all ios controlled by oe , regardless casl and cash . 27. self refresh mode is initiated by performing a cbr refresh cycle and holding ras low for the specified t rass . self refresh mode is terminated by rising ras high for a minimum time of t rps . 28. for all of the refresh mode expect the distributed cbr refresh mode, all rows must be refreshed within the refresh rate before and after self refresh. elite memory technology inc publication date : aug. 2005 revision : 1.4 6/16
elitemt m11l416256sa truth table addresses function ras elite memory technology inc publication date : aug. 2005 revision : 1.4 7/16 casl cash we oe row col dq s notes standby h h x h x x x x x high-z read : word l l l h l row col data-out read : lower byte l l h h l row col lower byte, data-out read : upper byte l h l h l row col upper byte, data-out write : word (early write) l l l l x row col data-in write : lower byte (early) l l h l x row col lower byte, data-in , upper byte, high-z write : upper byte (early) l h l l x row col lower byte, high-z , upper byte, data-in read-write l l l h l l h row col data-out, data-in 1, 2 1st cycle l h l h l h l row col data-out 2 2nd cycle l h l h l h l col data-out 2 edo-page-mode read any cycle l l h l h h l data-out 2 1st cycle l h l h l l x row col data-in 1 edo-page-mode write 2nd cycle l h l h l l x col data-in 1 1st cycle l h l h l h l l h row col data-out, data-in 1, 2 edo-page-mode read-write 2nd cycle l h l h l h l l h col data-out, data-in 1, 2 hidden refresh l h l l l h l row col data-out 2 ras -only refresh l h h x x row high-z cbr refresh h l l l h x x x high-z 3 self-refresh h l l l h x x x high-z 3 *note : 1. these write cycles may also be byte write cycles (either casl or cash active). 2. these read cycles may also be byte read cycles (either casl or cash active). 3. only one cas must be active ( casl or cash ).
elitemt m11l416256sa read cycle ras v ih v il casl,cash v ih v il v ih v il addr v ih v il we v oh v ol i/o v ih v il oe t rc t ras t rp row column valid data row t crp t csh t rsh t cas t clch t rrh open open t off2 t oac t clz t cac t rcs t rac t aa t off1 note1 t asr t rah t asc t cah t rad t ral t ar t rcd t rch valid data ras casl,cash addr t rc t ras t rp row column row t crp t csh t rsh t cas t clch t cwl t wp t wch t asr t rah t asc t cah t rad t ral t ar t rcd t rwl t wcr t wcs t dh t ds t dhr we oe don't care undefined v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il i/o early write cycle note: 1. t off1 is referenced from the rising edge of ras or cas , whichever occurs last. elite memory technology inc publication date : aug. 2005 revision : 1.4 8/16
elitemt m11l416256sa ras v ih v il casl,cash v ih v il v ih v il addr v ih v il we v i/oh v i/ol i/o v ih v il oe t rwc t ras t rp row column row t crp t csh t rsh t cas, t clch open t dh t off2 t clz t cac t rcs t rac t aa t asr t rah t asc t cah t rad t ral t ar t rcd t cwl ras casl,cash addr t rp row t crp t cp t cas, t clch t rah t asc t cah t rad t ar t rcd we oe don't care undefined v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il i/o t rwl t wp t awd t rwd t cwd valid d out t ds t oeh t oac row t asr t cah t asc t cah t asc t csh column t cp t pc (note2) column t ral t cas, t clch t rsh t cp column t rcs t rrh t rch valid data valid data t cac t clz t rac t aa t cac t coh t acp t aa t cac t clz t acp t aa valid data open note1 t off1 open t oac t oes t off2 t oehc t oac t oes t oep t off2 t rasc valid d in t cas, t clch edo-page-mode read cycle read write cycle ( late write and read-modify-write cycles ) *note : 1. t off1 is referenced from the rising edge of ras or cas , whichever occurs last. 2. t pc can be measured from falling edge of cas to falling edge of cas , or from rising edge of cas to rising edge of cas . both measurements must meet the t pc specification. elite memory technology inc publication date : aug. 2005 revision : 1.4 9/16
elitemt m11l416256sa edo-page-mode early-write cycle ras v ih v il casl,cash v ih v il v ih v il addr v ih v il we v ih v il i/o v ih v il oe t rasc t rp t crp t ds t wcs t dhr t wcr t asr t rah t asc t cah t rad t ar t cwl ras casl,cash addr we oe don't care undefined v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol v ih v il i/o t wch t wp t wp t cwl t wch column row t cp t cas, t clch t rcd t csh t cas, t clch t cp t pc (note1) t cas, t clch t cp t rsh t asc t cah column t asc t cah column t ral row t wcs t wp t cwl t wch t wcs valid data t dh t ds t dh t ds t dh t rwl t rasc t rp t crp t rcs t asr t rah t asc t cah t rad t ar t cwd t rwd t awd t cas, t clch t rcd t csh t cas, t clch t cp t pcm t cas, t clch t cp t rsh t asc t cah t asc t cah t ral t cp row t cwl t wp t cwd t awd t cwl t wp t cwd t awd t cwl t wp t rwl t clz t cac t ds t dh valid d out valid d in t rac t aa valid d out valid d in t clz t cac t ds t dh t aa t acp t aa t acp t clz t cac t ds t dh valid d out t oac t oac t off 2 t oac t off2 t oeh valid d in t off2 valid data valid data column column column row edo-page-mode read-write cycle (late write and read-modify-write cycles) note : 1. t pc can be measured from falling edge to falling edge of cas , or from rising edge to rising edge of cas . both measurements must meet the t pc specification. elite memory technology inc publication date : aug. 2005 revision : 1.4 10/16
elitemt m11l416256sa edo-page-mode read-early-write cycle (psuedo read-modify-write) ras v ih v il v ih v il v ih v il addr v ih v il we v i/oh v i/ol i/o v ih v il oe ras casl,cash addr don't care undefined v ih v il v ih v il v ih v il v oh v ol i/o t rp row t crp t cp t cas t pc t rah t asc t cah t rad t ar t rcd row t asr t cah t asc t cah t asc t csh column(b) t cp t cas t cp column(n) t ral t cas t cp column(a) t rcs t rch t wcs valid data(b) t cac t rac t aa t cac t asr t aa t whz open t oac t ds t rasc t wch valid data in valid data(a) t coh t dh t rsh t ras t rc t rpc t crp row row t rah open t acp t rp casl,cash ras only refresh cycle (addr = a0~a8 ; oe , we = don?t care) elite memory technology inc publication date : aug. 2005 revision : 1.4 11/16
elitemt m11l416256sa cbr refresh cycle (a0~a8 ; oe = don?t care) ras v ih v il casl,cash v ih v il v ih v il we i/o ras casl,cash addr v ih v il v ih v il v ih v il v oh v ol i/o t rpc t rp (read) t ras t rp (refresh) t ras t chr t cp t csr t csr t chr t rpc t rp t chr t ras open t rsh t crp t rcd row column t asr t rah t asc t rad t cah t ral t ar valid data open open t aa t rac t cac t clz note1 t off1 v ih v il oe t oac t ord t off2 don't care undefined t ras t rch hidden refresh cycle ( we = high ; oe = low) note : 1. t off1 is reference from the rising edge of ras or cas , whichever occurs last. elite memory technology inc publication date : aug. 2005 revision : 1.4 12/16
elitemt m11l416256sa self refresh cycle ( oe = don?t care) ras casl,cash addr v ih v il v ih v il v ih v il v oh v ol i/o t chs open t rp t rass t rps we v ih v il t cp t csr t rpc t rch t rpc t crp t asr don't care undefined elite memory technology inc publication date : aug. 2005 revision : 1.4 13/16
elitemt m11l416256sa packing dimensions 40-lead soj(400mil) section i 40 21 1 20 d e 1 e seating plain a 2 b 2 b 0 . 0 5 0 " m a x . e e 2 0.024" min. a 1 a 1 r 1 c detail "a" detail "a" section ii 40 21 1 20 d e 1 e seating plain a 2 b 2 b 0 . 0 5 0 " m a x . e e 2 0.024" min. a 1 a 1 r 1 c detail "a" detail "a" symbol dimension in mm dimension in inch symbol dimension in mm dimension in inch min norm max min norm ma x min norm max min norm max a 3.250 3.510 3.760 0.128 0.138 0.148 e 10.920 11.176 11.430 0.430 0.440 0.450 a 1 2.080 0.082 e 1 10.030 10.160 10.290 0.395 0.400 0.405 a 2 2.790 ref 0.110 ref e 2 9.40 bsc 0.370 bsc b 0.380 0.460 0.560 0.015 0.018 0.022 r 1 0.760 0.890 1.020 0.030 0.035 0.040 b 2 0.635 ref 0.025 ref 1 0 10 0 10 c 0.180 0.250 0.360 0.007 0.010 0.014 d 25.91 26.040 26.290 1.02 1.025 1.035 e 1.270 bsc 0.050 bsc elite memory technology inc publication date : aug. 2005 revision : 1.4 14/16
elitemt m11l416256sa packing dimensions 40 / 44-lead tsop(ii) dram(400mil) symbol dimension in mm dimension in inch min norm max min norm max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.042 b 0.30 0.45 0.012 0.018 b1 0.30 0.35 0.40 0.012 0.014 0.016 c 0.12 0.21 0.005 0.008 c1 0.10 0.16 0.004 0.006 d 18.28 18.41 18.54 0.720 0.725 0.730 zd 0.805 ref 0.0317 ref e 11.56 11.76 11.96 0.455 0.463 0.471 e1 10.03 10.16 10.29 0.395 0.400 0.4 l 0.40 0.59 0.69 0.016 0.023 0.027 l1 0.80 ref 0.031 ref e 0.80 bsc 0.0315 bsc o ~ ref 7 o ~ ref 7 elite memory technology inc publication date : aug. 2005 revision : 1.4 15/16
elitemt m11l416256sa elite memory technology inc publication date : aug. 2005 revision : 1.4 16/16 important notice all rights reserved. no part of this document ma y be reproduced or duplicated in any form or by any means without the prior permission of elitemt. the contents contained in this document ar e believed to be accurate at the time of publication. elitemt assumes no responsibility for any erro r in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presen ted only as a guide or examples for the application of our products. no respons ibility is assumed by elitemt for any infringement of patents, copyr ights, or other intellectua l property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elitemt or others. any semiconductor devices ma y have inherently a cert ain rate of failure. to minimize risks associated with custom er's application, adequate design and operating safeguards against injury, damage , or loss from such failure, should be provided by the customer when making application designs. elitemt's products are not authorized for us e in critical applications such as, but not limited to, life support devices or system , where failure or abnormal operation may directly affect human lives or cause physi cal injury or property damage. if products described here are to be us ed for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.

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